The candidate will work as part of a radio design team interacting closely with systems, software and RF front end engineers to develop a novel RRH solution. He/she will be a key contributor in full cycle product development – design, development, integration, field test and interoperability support – and will also be a core contributor to fine tune performance of complex interactions between FW/SW/HW on FPGAs and processors running Linux/embedded RTOS. This is a unique opportunity to work on development for a ground-breaking wireless communications system. Specific responsibilities include:
- Perform detailed FPGA design and verification using Verilog / VHDL and commercial tool sets for further analysis with interface / timing constraints.
- Contribute to algorithmic analysis and architecture specification for Communication and DSP blocks of a digital front end LTE remote radio head
- Work with systems architects and hardware engineers to develop/implement and test robust radio signal processing algorithms
- Support RTL Verification including proactive contributions on test plans, generation of test vectors and issue debug
- Integration of third party IP digital blocks
- Test/Verification of Field Test System
- 5+ years experience required in FPGA and RTL including hardware description languages (Verilog, System Verilog, VHDL), FPGA synthesis, IP integration, functional verification, timing analysis, constrains and design rule checks
- Knowledge of QuestaSim and familiarity with Vivado Design Suite is highly desirable.
- Ability to write effective test benches, collect results, and prepare feedback reports for the design engineers
- Development of RTL blocks in support of wireless communications is essential including experience in CPRI implementations is highly desirable
- Familiarity Xilinx and/or Altera SoC devices with integrated ARM cores and their kits
- Understand interconnect protocols like AHB/AXI and DMA concepts
- Knowledge of DSP and digital communication theory is desirable.
- Practical implementation of the following blocks: digital filter, DUC/DDC, CFR, digital equalizers, DPD, AGC, fixed point DSP.
- Familiarity with IO interfaces such as CPRI, SPI, I2C, PCI/e and other standard bus protocols
- Familiarity with C, Linux and scripting languages (perl /TCL/csh) and Matlab is highly desirable
- Ability to work from system requirements and architecture documents to develop signal processing blocks and interface designs that meet those requirements
- Ability to clearly document architecture, design, and interface specifications
- A Bachelor’s degree in in Computer Engineering/Electrical Engineering is required. A Master’s degree is strongly preferred.
We offer benefits that are competitive and comprehensive including the following:
- Performance-based annual bonus
- 401K with performance-backed employer match
- Early stage equity
- Medical, dental and vision care programs
- Flexible and subsidized vacation policy
- Regular company-sponsored team lunches, unlimited beverages & snacks, etc.